1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication, and in particular, to fabricating both high density flash memory transistors and high performance logic transistors on the same semiconductor die.
2. Discussion of Related Art
Present semiconductor fabrication process technology may be used to generate discrete high density flash memory and high performance logic on separate wafers, and hence, separate chips. These two types of devices are not easily manufactured on the same wafer or on the same die.
FIG. 1 illustrates a logic transistor 100. Logic transistor 100 is formed on substrate 102. The gate stack of logic transistor 100 consists of a gate electrode layer 106 deposited over the gate dielectric 104 on substrate 102. Source/drain spacer liner dielectric 108 is formed on either side of the gate stack. Source/drain spacer dielectric 110 is formed on either side of the gate stack on top of the source/drain spacer liner dielectric 108.
FIG. 2 illustrates a flash memory transistor 200. Flash memory transistor 200 is formed on substrate 102. The gate stack of flash memory transistor 200 consists of a control gate electrode layer 113 deposited over an inter-electrode dielectric 112, over a floating gate layer 111, over the gate dielectric 104, on a substrate 102. Source/drain spacer liner dielectric 108 is formed on either side of the flash memory gate stack. Source/drain spacer dielectric 110 is formed on either side of the gate stack on top of the source/drain spacer liner dielectric 108.
Because the flash memory gate stack is significantly different from the logic gate stack, separate gate patterning masking steps are required to enable the different etches required to etch each gate stack. However, patterning of one set of gates will create large topographic steps at the boundaries between the flash and logic regions, because the height of the flash gate stack is greater than the height of the logic gate stack. The topographic steps may lead to large lithographic proximity effects where there is poor control over the critical dimensions near the flash/logic boundaries.
Presently, both flash memory and logic transistors may be formed on the same die, however present semiconductor fabrication methods do not permit fabrication of both flash memory transistors having minimum critical dimensions and logic transistors having minimum critical dimensions on the same die. Large topographic steps formed between the flash gate stack and the logic gate stack lead to poor control over gate critical dimensions, thus only one of either flash or logic gates having minimum critical dimensions may be formed on a die.